Field of Invention
The present invention generally relates to a memory apparatus, and more particularly to a write assist circuit of the memory apparatus with negative bit line scheme.
Description of Prior Art
Referring to FIG. 1, FIG. 1 illustrates a schematic plot of a static random access memory (SRAM) cell. The SRAM cell 100 includes six transistors, and is coupled to a bit line BL, an inverted bit line BLB, and a word line WL. In a data writing operation, when a stored data at a node N1 is logic “1” and a write data with logic “0” is written to the node N1, the write data is carried on the bit line BL with logic “0”, and the transistor PG is turned on according to a signal on the word line WL. At the same time, the transistor PU is also turned on by a voltage on the node N2 with logic “0”. That is, the node N1 is discharge to logic “0” by the transistor PG, and is also charge to a power voltage VDD (logic “1”) by the transistor PU. It should be noted here, when driving abilities of the transistor PG is weaker than the transistor PU owing to process variation, a write-failure event can happen.